S12311
X120: 12x10G/40G/100G OTN & MACsec
The X12/X240 products integrate 100G Gearbox functionality with Ethernet PHY and OTN framer, delivering a cost and power optimized small foot print solution. The X120/X240 are ideal for high capacity Carrier Ethernet router/switches, Packet Optical Transport systems and DWDM Transport systems. Its integrated, high performance SerDes interfaces seamlessly with optical modules and direct attach copper cables. The X120/X240’s rich suite of Carrier Ethernet features, OTN mapping modes and provisional FEC ensure interoperability among multiple system OEMs. Highly integrated, low power 120 Gbps or 240 Gbps Smart PHY OTN processor device that supports up to 24-port 10G, 6-port 40G, or 2-port 100G Ethernet over OTN with MACsec, integrated Gearbox and 25G/28G CAUI-4/OTL4.4 interfaces.
Product Specifications
- Part Number
- S12311
- Description
- X120: 12x10G/40G/100G OTN & MACsec
- Max Serdes Rate(Gbps)
- 11.200
Features
- The DWDM OTN, EDC and high-gain FEC enables longer transmission distance
- Delivers industry leading high-gain, low latency enhanced FEC for 100G networks
- Features time stamping features for 1588v2 and Y.1731 OAM
- IEEE802.3AE compliant MACSec option provides a low cost, wire-rate security solution to data center and cloud based networks
- Fractional synthesizer and jitter attenuation PLLs are integrated to optimize total solution cost and enable high port density design
- IEEE802.3 compliant 10GE/40GE/100GE MAC and PCS, and mapping of Ethernet signal into OTU2/2e/1e, OTU3 and OTU4 digital wrapper signal
- IEEE standard compliant 1588 PTP timestamp and SyncE support to enable precise and accurate timing synchronization for Ethernet network
- IEEE 802.1AE compliant MACSec for 10GE, 40GE and 100GE to provide secured services
- Direct connection to XFP, SR/LR/ER/ZR and DWDM SFP+, QSFP+, CFP, CFP2, CFP4, QSFP28, 100G MSA optics and SFP+, QSFP+ Direct Attach Copper modules
- Interlaken system packet interface
- I/O cross-connect on high speed I/O supports protection switching and eases PCB design
- Tri-FEC (G.709 RS-FEC, G.975.1 I.4 EFEC and I.7 UFEC) for 10G and 40G
- Integrated fractional synthesizer and jitter attenuation PLL enables single reference clock for all protocols and rates
- Extensive diagnostic features including in-system eye monitor for high speed I/Os, loopbacks, PRBS and Packet generators/checkers